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[VHDL-FPGA-Verilog] IDTContrl

Description: 该Verilog程序提供了一种控制IDT系列Ram的读写操作程序，每次读写750个16位的数。-The Verilog program control IDT provides a series of read and write operating procedures Ram, 750 each to read and write the number 16.
Platform: | Size: 1024 | Author: 刘进 | Hits:

[SCM] dual_ram

Description: FPGA和双端口RAM的DDS任意波形发生器的实现-FPGA and dual-port RAM of the DDS Arbitrary Waveform Generator
Platform: | Size: 513024 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] dds_easy

Description: 直接频率合成DDS模块的ise工程，可以直接下载，在Spartan3/Spartan3E上验证通过。该DDS模块可以产生双通道的不同频率的正弦波，也可以产生同频的任意相位差的相移波形。本模块累加器位数为32位，可以产生12位相位精度12位量化精度的正弦波。该设计例化一个Block Ram，为节省储存空间仅需要储存1/4周期的数据。根据需要，可以重新修改数据，改变波形。-DDS direct frequency synthesizer module ，ise project, can be directly downloaded through the Spartan3/Spartan3E and tested successfully. The DDS module can generate two-channel sine wave of different frequency, or produce the same frequency arbitrary waveform phase difference of the phase shift. There is a 32-bit accumulator to generate 12 bit phase-precision 12-bit quantization precision of the sine wave. Cases the design of a Block Ram, in order to save storage space need to store only 1/4 cycle of data. Necessary, can modify data, change the waveform.
Platform: | Size: 471040 | Author: 郭先生 | Hits:

[Other] ddpi_tx

Description: verilog语言编写的一个接口文件，使用乒乓ram-verilog language of an interface file, use the ping-pong ram
Platform: | Size: 1024 | Author: yaop | Hits:

[VHDL-FPGA-Verilog] bram_delay

Description: Verilog编写的代码，单口RAM用程序控制地址，而不是在仿真文件里面控制地址-Verilog code is written, single-port RAM with the process control address, rather than inside the control address of the simulation file
Platform: | Size: 1438720 | Author: niuniu | Hits:

[Other] rom_prf_gen

Description: 用ram存储顺序，用此方法也可以实现其他的顺序数据，代码用verilog编写-Ram memory with the order can be achieved using this method also the order of the other data, write code using verilog
Platform: | Size: 2048 | Author: zhm | Hits:

[VHDL-FPGA-Verilog] bubblesort1024ram

Description: 快速冒泡排序基于FPGA实现，有测试文件以及设计图，实现1024*32位数序的多数排序，突破传统是的REG类型少数排序，利用RAM，针对RAM中的无序数的地址调换，达到排序目的，仅供学习交流-Rapid bubble sort based on FPGA, there are test documents and design drawings to achieve 1024* 32-digit sequence of the majority of sorting, breaking tradition is a REG types of minority sorting, the use of RAM, the disorder for the RAM address of the number of exchange, to sort purpose, only to learn the exchange of.
Platform: | Size: 5120 | Author: 柳泽明 | Hits:

[Other] verilog_RAM

Description: verilog 实现的一个双口RAM及其控制模块.我通过先存入64个数据在读出仿真通过。-verilog implementation of a dual-port RAM.
Platform: | Size: 1024 | Author: 世海 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 压缩包中包含了用Verilog编写的视频控制模块，实现PAL制式到VGA制式的实时转换，同时包含了VGA专用ram配置模块，可直接实用-Compressed package includes the preparation of the video with the Verilog control module, PAL format to achieve real-time conversion to standard VGA, VGA also includes dedicated ram configuration module can be directly useful
Platform: | Size: 79872 | Author: 熊文 | Hits:

[VHDL-FPGA-Verilog] shift_regeister

Description: 用blockram实现移位寄存器，开发语言为verilog hdl-Shift register with blockram achieve the development language for the verilog hdl
Platform: | Size: 148480 | Author: 郭淮 | Hits:

[VHDL-FPGA-Verilog] using_the_block_RAM_in_Spartan-3_FPGA

Description: Spartan-3 系列 FPGA 中的 Block RAM 的使用-using the block RAM in Spartan-3 FPGA
Platform: | Size: 32768 | Author: lishiwei | Hits:

[VHDL-FPGA-Verilog] dual_RAM

Description: actel fusion startkit FPGA开发板试验例程，可实现2k8的双口ram，实现数据存储，缓冲。包含verilog HDL 语言源码-actel fusion startkit FPGA development board test routines, can be realized 2k8' s dual-port ram, achieving data storage, buffer. Language source code contains the verilog HDL
Platform: | Size: 608256 | Author: zhangyujun | Hits:

[VHDL-FPGA-Verilog] blk_write

Description: verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
Platform: | Size: 2048 | Author: y_gt | Hits:

[VHDL-FPGA-Verilog] LIP2321CORE_cpu_local_ram

Description: CPU Local RAM Verilog Module
Platform: | Size: 28672 | Author: jc | Hits:

[Embeded-SCM Develop] LIP2301CORE_Synthesisable-RAM

Description: Verilog Synthesisable RAM source code
Platform: | Size: 214016 | Author: jc | Hits:

[VHDL-FPGA-Verilog] NET2

Description: This file with the wavelet transf Mallat implementation of wavelet Verilog hdl code modules for radi Modelsim 6.6 crack, can be used f A written using Verilog DDR2 cont Simple CPU VHDL implementation an Dual-port RAM design, using Veril Verilog language, a hardware-base FPGA embedded project combat, Man Application FPGA, FPGA-chip hardw Mallat implementation of wavelet Layer of one-dimensional wavelet
Platform: | Size: 1852416 | Author: sansfroid | Hits:

[VHDL-FPGA-Verilog] ssram

Description: 同步静态RAM读写程序，可用作模块，已通过ISE12.4验证-Synchronous Static RAM read and write procedures, can be used as modules, have been verified by ISE12.4
Platform: | Size: 1024 | Author: koo | Hits:

[VHDL-FPGA-Verilog] AMBA-Bus_Verilog_Model

Description: 该源码包是2.0版本的AMBA总线的Verilog语言模型，主要包括5个部分：AHB总线仲裁器，AHB-APB总线桥接器，AHB总线上从设备ROM模型，AHB总线上从设备RAM模型，参数定义。-This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.
Platform: | Size: 17408 | Author: jinjin | Hits:

[VHDL-FPGA-Verilog] ram

Description: 利用verilog实现的双口RAM。文件包含工程文件，仿真文件，使用方便。-Using verilog implementation of dual-port RAM. File contains the project files, simulation files, easy to use.
Platform: | Size: 219136 | Author: sue | Hits:

[VHDL-FPGA-Verilog] true_dual_port_ram_dual_clock

Description: 双端口ram的verilog程序，经过验证，可编译可用,-dual pot ram
Platform: | Size: 1024 | Author: lee | Hits:
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